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用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
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这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communicatio
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dsp5416与tl16c550实现并口转串口通信程序-dsp5416 with tl16c550 achieve Parallel to Serial Communication Program
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并口开发实用工具的文档和源码，已根据此开发出并口调试I2C的实用工具。-Parallel to the development of practical tools and source files, this has developed parallel debugging I2C a practical tool.
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针对数字高频头芯片设计的IIC并口转串口通信协议源代码。-digital tuner chip design IIC parallel to serial communications protocol source code.
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该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel c
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一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
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soft Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter : needs I and Q components of QPSK symbols at the input,soft Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial
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并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
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it gives serial in parallel out code for ofdm in matlab
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该模块实现的是并串转换功能，经过仿真验证没有问题-This module is designed to implement parallel to serial conversion
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it s a code for parallel to serial data
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串口大并口的通讯proteus程序及keil asm工程-Large parallel proteus serial communication procedures and keil asm Engineering
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并口到串口的通讯 proteus及keil asm工程文件-Parallel to serial communications and keil asm project file proteus
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Parallel interface to serial interface -Parallel interface to serial interface
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基于VERILOG的并行转串行程序-Based on the parallel to serial procedures VERILOG
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verilog语言 12位串行数据传输转换为并行传输-12bit parallel to serial decoder and aynthesis result
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This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.
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用Verilog语言编程实现并行转串行，并在modelsim中仿真出波形。-programming to realize parallel to serial using Verilog language , and simulating waveform in the modelsim.
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Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
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